Manufacturers of semiconductor devices face constant pressure to reduce the number of interconnects, especially in chipset platforms comprising multiple semiconductor devices interconnected on a common printed circuit board. Since the number of pins is a major factor in the costs of inter-chip connections, it is desirable to make such interconnects fast and narrow. This has led to the development of devices having fewer pins, and pins that can transmit signals very quickly.
One proposal addressing this problem is to utilize a half-duplex bus with distributed arbitration for I/O interconnects designed to connect I/O hubs and peripheral component interface (PCI) bridges (e.g., south bridges) to the memory hub controller (e.g., north bridge). It is well known that in a full-duplex bus, traffic can flow bi-directionally, simultaneously across separate sets of wires. A half-duplex bus is one in which there is a single lane of traffic (i.e., one set of wires) that is shared according to some sort of time-multiplexing scheme. A useful analogy is to think of a half-duplex bus as a single-lane bridge spanning across a river or chasm. Flagman positioned at each end signal to the other side to request ownership or use of the bridge in order to allow traffic to traverse in one direction or the other.
A common method to achieve synchronization on a half-duplex bus is via a global clock, also frequently referred to as a common or base clock. Each agent coupled to the bus usually has its own associated request signal line (REQ) used to gain ownership of the bus. Since traffic flow over the bus is always unidirectional, only one side of the bus has ownership of the bus at any given time. Each agent executes the same arbitration algorithm; asserting its request signal to convey its request to a remote agent; sampling the request signal driven by the remote agent; and then choosing which agent to grant ownership to based on the local and remote requests. Thus, in a half-duplex bus link, both ends contend for the shared bus resource.
In a typical I/O environment in which a half duplex a bus is deployed, one end of the link usually connects to a memory controller. The vast majority of traffic comprises memory reads and writes generated by devices connected to the I/O bridge and targeting the memory coupled to the memory controller. In such a system, three types of requests normally contend for ownership of the link: (1) write transfers (address plus data) upstream to the memory controller; (2) read requests (address plus size); and (3) read returns (address plus data) downstream to the requesting agent.
Data writes and read returns are very similar in that the both have a long latency and both are unidirectional “fire and forget” transfers. But a memory read operation is quite different. A successful memory read operation requires a complete round-trip over the bridge; that is, a read request must first travel upstream to the memory controller, where the request is serviced, followed by a return of the read data downstream back to the requesting agent.
The rate of read returns is often limited by the rate at which read requests travel upstream. Under heavy loading conditions, particularly involving many downstream read returns, there can be a long delay before traffic flow across the link is turned around to permit an upstream read request. If the latency period is too long, the memory controller will run out of pending requests, and thus experience a momentary break in the pipelining of read returns. Failure to allow a read request upstream in a timely manner can therefore result in a “bubble” in the read return traffic, with a corresponding reduction in read bandwidth.
Accordingly, what is needed is a method or protocol that permits more efficient utilization of the half-duplex bus resource.